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SMARTSWITCH
TM
BLOCK DIAGRAM & PIN CONFIGURATIONS
36 x 24 Dot Matrix
11
10
V LC
V DD
LCD Panel
seg1 seg36
5
7
FLM
SCP
Timing Control
Segment Driver
6
LP
CK
40bit Latch
8
Din
CK 40bit
D Shift RegisterQ
4
Dout
9
GND
SW
1
2
SW
12
BL-LED (+)
3
13
BL-LED (– )
NC
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
Symbol
SW
SW
BL-LED (–)
Dout
FLM
LP
SCP
Din
GND
V DD
V LC
BL-LED (+)
NC
Name
Terminal of Switch
Terminal of Switch
Terminal of Backlight LED
Data Output
First Line Marker
Latch Pulse
Serial Clock Pulse
Data Input
Ground
Power
Power
Terminal of Backlight LED
None
Function
Normally open
Normally open
Cathode
Display serial output. Can be used to connect to Din of the next SMARTSWITCH. As a result,
many SMARTSWITCHES can be controlled with one clock and data signal.
The marking signal for the first line data of LCD display. The first line of LCD will be selected
by the falling edge of LP signal during the high level (FLM).
Line data latch pulse will latch content of internal 40-bit shift register at falling edge for one
line of display. LP will also increment the display line by one.
Clock used by 40-bit internal shift register of the switch, shifting the display data bit presented
at Din at falling edge.
Display serial data bit. Note: to map the display data, because of the difference between the
number of internal shift register data (40) and the single line of LCD pixels (36), the first four
bits of data shifted will be dummy bits.
Power source for logic circuit
Power source for LCD drive
Anode for common
No Connection
NKK Switches ? email: smartswitch@nkkswitches.com ? Phone (480) 991-0942 ? Fax (480) 998-1435 ? www.nkksmartswitch.com
3
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